ADT7490
Table 108. REGISTER 0x8F ? DYNAMIC T MIN CONTROL REGISTER 2 (POWER-ON DEFAULT = 0x00)
Bit No.
[2:0]
[5:3]
[7:6]
Mnemonic
CYR1
CYL
CYR2
R/W (Note 1)
R/W
R/W
R/W
Description
3-bit Remote 1 Cycle Value. These three bits define the delay time between making
subsequent T MIN adjustments in the control loop for the Remote 1 channel in terms of
number of monitoring cycles. The system has associated thermal time constants that need to
be found to optimize the response of fans and the control loop.
Bit Code
Decrease Cycle
Increase Cycle
000
8 cycles (1 sec)
16 cycles (2 sec)
001
16 cycles (2 sec)
32 cycles (4 sec)
010
32 cycles (4 sec)
64 cycles (8 sec)
011
64 cycles (8 sec)
128 cycles (16 sec)
100
128 cycles (16 sec)
256 cycles (32 sec)
101
256 cycles (32 sec)
512 cycles (64 sec)
110
512 cycles (64 sec)
1024 cycles (128 sec)
111
1024 cycles (128 sec)
2048 cycles (256 sec)
3-bit Local Temperature Cycle Value. These three bits define the delay time between making
subsequent T MIN adjustments in the control loop for the local temperature channel in terms of
number of monitoring cycles. The system has associated thermal time constants that need to
be found to optimize the response of fans and the control loop.
Bit Code
Decrease Cycle
Increase Cycle
000
8 cycles (1 sec)
16 cycles (2 sec)
001
16 cycles (2 sec)
32 cycles (4 sec)
010
32 cycles (4 sec)
64 cycles (8 sec)
011
64 cycles (8 sec)
128 cycles (16 sec)
100
128 cycles (16 sec)
256 cycles (32 sec)
101
256 cycles (32 sec)
512 cycles (64 sec)
110
512 cycles (64 sec)
1024 cycles (128 sec)
111
1024 cycles (128 sec)
2048 cycles (256 sec)
2 LSBs of 3-bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in the Dynamic
T MIN Control Register 1 (Register 0x8E). These three bits define the delay time between
making subsequent T MIN adjustments in the control loop for the Remote 2 channel in terms
of number of monitoring cycles. The system has associated thermal time constants that need
to be found to optimize the response of fans and the control loop.
Bit Code
Decrease Cycle
Increase Cycle
000
8 cycles (1 sec)
16 cycles (2 sec)
001
16 cycles (2 sec)
32 cycles (4 sec)
010
32 cycles (4 sec)
64 cycles (8 sec)
011
64 cycles (8 sec)
128 cycles (16 sec)
100
128 cycles (16 sec)
256 cycles (32 sec)
101
256 cycles (32 sec)
512 cycles (64 sec)
110
512 cycles (64 sec)
1024 cycles (128 sec)
111
1024 cycles (128 sec)
2048 cycles (256 sec)
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to this
register fail.
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